2.1.4 DDR3

The DDR3 subsystem is configured to access the 16-bit DDR3 memory through an AXI4 interface. The PolarFire Evaluation's Kit DDR3 memory preset is applied to configure all the memory initialization and timing parameters in the DDR configurator. The following figure shows general configuration settings of the DDR3 memory.

Figure 2-11. DDR3 Configuration
Important: For more information about Rev E or later Kit DDR3 Configurations (MT41K512M8DA-107: P), see Appendix 3 - DDR3 Configuration of the AN4997: PolarFire FPGA Building a Mi-V Processor Subsystem.