2.1.2 PF_SRAM_AHBL_AXI

This design uses three instances of PF_SRAM_AHBL_AXI core—pf_sram_0, PF_LSRAM_1_0, and PF_LSRAM_1_1.

The pf_sram_0 IP is connected to Mi-V as an AXI4 slave using Core AXI4Interconnect. The LSRAM blocks are initialized with the user application code from the external SPI Flash.

The processor uses the SRAM memory to execute the application. The following figure shows the LSRAM depth and the interface settings. The Fabric Interface type is selected AXI because the fabric interfaces with the Mi-V processor using Core AXI4Interconnect. The memory depth can be selected based on the application size. This design uses 512 KB RAM (131072 words).

The following figure show the PolarFire SRAM configuration.

Figure 2-5. PolarFire SRAM_0 Configuration

PF_LSRAM_1_0 and PF_LSRAM_1_1 are connected to the Mi-V AHBLite interface using CoreAHBLite. This memory (LSRAM_1_0 and LSRAM_1_1) is used for Ethernet MAC transmit and receive buffers.

The following figure show the PolarFire LSRAM configuration.

Figure 2-6. PolarFire LSRAM _1_0 Configuration