AN4569

2.1.5 PF_CCC_0

PF_CCC_0 (PolarFire Clock Conditioning Circuitry) generates the fabric reference clock that drives the soft processor and the APB peripherals. The PF_CCC_0 IP is configured to generate one output fabric clock from a 50 MHz input. The following figure shows the PF_CCC_0 input clock configuration.

Figure 2-12. PF_CCC_0 Input Clock Configuration

The following figure shows the PF_CCC_0 output clock configuration. The Mi-V processor supports up to 120 MHz. This design uses an 83.33 MHz system clock for configuring the APB peripherals.

Figure 2-13. PF_CCC_0 Output Clock Configuration

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