2.1.7 CORESPI_0

The CORESPI0 (CoreSPI) block is a controller IP that implements the serial communication. Mi-V configures the ZL30364 clock generation hardware using the CORESPI_0 block. The recommendations for CoreSPI configuration is provided in the following points, see Figure 2-15.

  • APB Data Width is selected as 32 because the design uses an APB data width of 32 bit.
  • The default serial protocol mode, Motorola mode is retained to interface with ZL30364.
  • Frame size is set to 16 to match the read/write cycles supported by ZL30364.
  • FIFO depth is set to 32 to store maximum frames (TX and RX) in FIFO.
  • The clock rate for the SPI master clock is selected as 7. This is used to generate the SPICLK, which is generated as PCLK/(2*(clock rate+1) = 83.33/(2*(7+1)).
  • The Keep SSEL active check box is enabled to keep the slave peripheral active between back-to-back data transfers.

The following figure shows the CoreSPI configuration.

Figure 2-15. CoreSPI_0 Configuration