2.1.1 Mi-V Soft Processor

The Mi-V soft processor supports RISC-V processor-based designs. The Mi-V soft processor executes the application from the LSRAM mapped at 0x80000000. It configures the ZL30364 clock generation hardware through the CoreSPI IP and the VSC PHY through CoreTSE_AHB MDIO interface. It also configures the CoreTSE_AHB registers using the AHB interface.

The following figure shows the Mi-V soft processor configuration, where the Reset Vector Address is set to 0x8000_0000. In Mi-V processor memory map, the memory range used for the AHB memory interface is 0x7000_0000 to 0x7FFF_FFFF, and the memory range used for the APB interface is 0x6000_0000 to 0x6FFF_FFFF.

Figure 2-3. Mi-V Configuration
Figure 2-4. Mi-V Memory Map