AN4569

2.1.3 CoreAXI4Interconnect

The AXI interconnect bus must be configured to connect the Mi-V core with memory. The following figure shows the bus configuration and other configuration of CoreAXI4Interconnect.

Figure 2-7. CoreAXI4Interconnect Configurator

Figure 2-8. CoreAXI4Interconnect Configurator-Master Configuration

Figure 2-9. CoreAXI4Interconnect Configurator-Slave Configuration

Figure 2-10. CoreAXI4Interconnect Configurator-Crossbar Configuration

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