18.4.6 Offset Calibration

This ADC requires an offset calibration. The hardware calibration procedure is executed:

• Each time when the ADC is enabled (ON bit = ‘1’ in ADnCON[15] )
• By a software request when the CALREQ bit (ADnCON[29]) is set.
• Periodically. The periodic recalibration is enabled when the ACALEN bit (ADnCON[28]) is set. The time between calibration cycles is selected by the CALRATE[1:0] bits, from a one second to a one hour period.

The CALRDY bit (ADnCON[30]) indicates the calibration status. This bit is set by hardware when the calibration cycle is finished and the hardware clears it when the calibration is in progress.

The calibration has lowest priority and is delayed when a conversion is in progress. The ADC must be idle for a few ADC clock cycles to start the calibration. This idle time is set by the CALCNT[1:0] bits.

The initial power-on calibration requires about 5000 ADC clock cycles, but recalibration requested by the software using the CALREQ bit, or recalibration done periodically when the ACALEN bit is set, takes about 10 ADC clock cycles.