18.4.14 Calibration

The startup hardware calibration procedure is executed each time the ADC is enabled via setting the ON bit (ADnCON[15]). The startup calibration procedure includes both gain and offset adjustment. The CALRDY bit (ADnCON[30]) status bit provides indication that the process is complete. CALRDY is set by hardware when the calibration cycle is finished, and the hardware clears this bit when the calibration is in progress. The startup calibration takes about 5000 ADC clock cycles.

The ADC offset may drift slightly across temperature. The ADC has hardware to run the offset calibration. The offset calibration procedure takes 14 T_AD cycles and can be executed using one of the following methods:

• A software request by setting the CALREQ bit (ADnCON[29]).
• Automatic, periodically. The periodic recalibration is enabled by the ACALEN bit (ADnCON[28]). The time between calibration cycles is set with the CALRATE[1:0] bits from times ranging from 1 second to 1 hour.

The offset calibration has the lowest priority, and it is delayed when a conversion is in progress. The ADC must idle a few ADC clock cycles to start the calibration. This idle time is set by CALCNT[1:0] bits.