18.4.10 Result Formatting
The result of a single conversion (MODE[1:0] bits = ‘00’) is stored in the
ADnCHxDATA register. For the multiple conversion modes (MODE[1:0] !=
‘00’), the results are added to an internal primary accumulator.
The result sum is copied from the primary accumulator to the ADnCHxDATA register when
the corresponding CHxRDY bits are set.
The value in the ADnCHxDATA register is formatted using DIFF and LEFT bit settings (ADnCHxCON[15] and ADnCHxCON[10]). The format options are explained in Table 18-22.
| Differential Format Option DIFF bit | Input Voltage | Result in ADnCHxDATA Register | |||
|---|---|---|---|---|---|
| (VINP = Voltage on non-inverting input, VINN = Voltage on inverting input) | LEFT bit = 0 | LEFT bit = 1 | |||
| Decimal | Hex | Decimal | Hex | ||
| 0 | VINP = 0 | 0 | 0000 0000 | 0 | 0000 0000 |
| VINP = VDD/2 | +2047 | 0000 07FF | +2,146,435,072 | 7FF0 0000 | |
| VINP ≥ VDD | +4095 | 0000 0FFF | +4,293,918,720 | FFF0 0000 | |
| 1 | VINP – VINN ≦ – VDD | -2048 | FFFF F800 | -2,147,483,648 | 8000 0000 |
| VINP – VINN = -VDD/2 | -1024 | FFFF FC00 | -1,073,741,824 | C000 0000 | |
| VINP – VINN = 0 | 0 | 0000 0000 | 0 | 0000 0000 | |
| VINP – VINN = VDD/2 | +1023 | 0000 003FF | +1,072,693,248 | 3FF0 0000 | |
| VINP – VINN ≥ VDD | +2047 | 0000 007FF | +2,146,435,072 | 7FF0 0000 | |