18.4.3 Sampling and Conversion Timing

Each channel can be configured for a different sampling time using the SAMC[2:0] bits (ADnCHxCON[7:5]), ranging from 6.25 nS to 181.25 nS.

The input ADC module clock is divided by four to get the analog ADC core clock (TAD). 1.5 ADC clock cycles are needed to complete the conversion.