10.1.1 FCP Configuration Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | FCP |
| Offset: | 0x7F3000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WPUCA[1:0] | CRC | CP | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 1 | 1 | 1 | |||||
Bits 3:2 – WPUCA[1:0] Write Protect bits
| Value | Description |
|---|---|
| 11 | UCA1 and UCA2 not write protected |
| 10 | Reserved |
| 01 | UCA1 and UCA2 write protected |
| 00 | Reserved |
Bit 1 – CRC Code Protect User Program CRC bit
| Value | Description |
|---|---|
1 | CRC is disallowed in test modes when code protection is enabled |
0 | CRC is allowed in test modes when code protection is enabled |
Bit 0 – CP Code Protect Enable bit
| Value | Description |
|---|---|
1 | Code protection disabled |
0 | Code protection is enabled |