10.1.4 FWDT Configuration Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | FWDT |
| Offset: | 0x0x7F3030 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WDTRSTEN | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WDTEN | WDTWIN[1:0] | RWDTPS[4:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RCLKSEL[1:0] | SWDTPS[4:0] | WINDIS | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | |
Bit 16 – WDTRSTEN WDT Reset Enable bit
| Value | Description |
|---|---|
1 | Enables WDT Reset; run time WDT event will cause a device Reset |
0 | Disables WDT Reset; run time WDT event generates a trap |
Bit 15 – WDTEN Watchdog Timer Enable bit
| Value | Description |
|---|---|
1 | WDT is enabled in hardware |
0 | WDT controlled via the ON bit (WDTCONL[15]) |
Bits 14:13 – WDTWIN[1:0] Watchdog Timer Window Select bits
| Value | Description |
|---|---|
11 |
WDT window is 25% of the WDT period |
10 |
WDT window is 37.5% of the WDT period |
01 |
WDT window is 50% of the WDT period |
00 |
WDT Window is 75% of the WDT period |
Bits 12:8 – RWDTPS[4:0] Run Mode Watchdog Timer Period Select bits
| Value | Description |
|---|---|
11111 | Divide by 2 ^ 31 = 2,147,483,648 |
11110
| Divide by 2 ^ 30 = 1,073,741,824 |
... | |
00001 | Divide by 2 ^ 1 = 2 |
00000 | Divide by 2 ^ 0 = 1 |
Bits 7:6 – RCLKSEL[1:0] Watchdog Timer Clock Select bits
| Value | Description |
|---|---|
11 |
LPRC clock |
10 |
Uses BFRC when system clock is not INTOSC/LPRC and device is not in sleep; otherwise, uses INTOSC/LPRC |
01 |
Reserved |
00 |
Uses peripheral clock (FOSC/4) when device is not in sleep; otherwise, uses LPRC |
Bits 5:1 – SWDTPS[4:0] Sleep Mode Watchdog Timer Period Select bits
| Value | Description |
|---|---|
11111 | Divide by 2 ^ 31 = 2,147,483,648 |
11110 | Divide by 2 ^ 30 = 1,073,741,824 |
| ... | |
00001 | Divide by 2 ^ 1 = 2 |
00000 | Divide by 2 ^ 1 = 2 |
Bit 0 – WINDIS Watchdog Window Disable bit
| Value | Description |
|---|---|
| 1 | Window mode disabled |
| 0 | Window mode enabled |