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10.1.2 FICD Configuration Register
Table 10-6. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: FICD Offset: 0x7F3010
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 Reserved JTAGEN Access R/W R/W Reset 1 0
Bit 7 – Reserved Reserved: Maintain as
‘1’
Bit 5 – JTAGEN JTAG Enable bit Value Description 1JTAG port is
enabled 0JTAG port is
disabled
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