20.3.3 QEI Status Register
Note:
- This status bit is only applicable
to PIMOD[2:0] modes, ‘
011’ and ‘100’.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | QEI1STAT |
| Offset: | 0x1A08 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCHEQIRQ | PCHEQIEN | PCLEQIRQ | PCLEQIEN | POSOVIRQ | POSOVIEN | ||||
| Access | R/W/HS | R/W | R/W/HS | R/W | R/W/HS | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PCIIRQ | PCIIEN | VELOVIRQ | VELOVIEN | HOMIRQ | HOMIEN | IDXIRQ | IDXIEN | ||
| Access | R/W/HS | R/W | R/W/HS | R/W | R/W/HS | R/W | R/W/HS | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 13 – PCHEQIRQ Position Counter Greater Than Compare Status bit
| Value | Description |
|---|---|
1 | POSxCNT > QEIxGEC |
0 | POSxCNT < QEIxGEC |
Bit 12 – PCHEQIEN Position Counter Greater Than Compare Interrupt Enable bit
| Value | Description |
|---|---|
1 | Position Counter Greater Than Compare interrupt is enabled |
0 | Interrupt is disabled |
Bit 11 – PCLEQIRQ Position Counter Less Than Compare Status bit
| Value | Description |
|---|---|
1 | POSxCNT < QEIxLEC |
0 | POSxCNT > QEIxLEC |
Bit 10 – PCLEQIEN Position Counter Less Than Compare Interrupt Enable bit
| Value | Description |
|---|---|
1 | Position Counter Less Than Compare interrupt is enabled |
0 | Interrupt is disabled |
Bit 9 – POSOVIRQ Position Counter Overflow Status bit
| Value | Description |
|---|---|
1 | Position Counter Overflow has occurred |
0 | Position Counter Overflow has not occurred |
Bit 8 – POSOVIEN Position Counter Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 | Position Counter Overflow interrupt is enabled |
0 | Position Counter Overflow interrupt is disabled |
Bit 7 – PCIIRQ Position Counter (Homing) Initialization Process Complete Status bit(1)
| Value | Description |
|---|---|
1 | POSxCNT was reinitialized |
0 | POSxCNT was not reinitialized |
Bit 6 – PCIIEN Position Counter (Homing) Initialization Process Complete Interrupt Enable bit
| Value | Description |
|---|---|
1 | Position Counter (Homing) Initialization Process Complete interrupt is enabled |
0 | Position Counter (Homing) Initialization Process Complete interrupt is disabled |
Bit 5 – VELOVIRQ Velocity Counter Overflow Status bit
| Value | Description |
|---|---|
1 | Velocity Counter Overflow has occurred |
0 | Velocity Counter Overflow has not occurred |
Bit 4 – VELOVIEN Velocity Counter Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 | Velocity Counter Overflow interrupt is enabled |
0 | Velocity Counter Overflow interrupt is disabled |
Bit 3 – HOMIRQ Home Event Status bit
| Value | Description |
|---|---|
1 | Home event has occurred |
0 | No home event has occurred |
Bit 2 – HOMIEN Home Input Event Interrupt Enable bit
| Value | Description |
|---|---|
1 | Home input event interrupt is enabled |
0 | Home input event interrupt is disabled |
Bit 1 – IDXIRQ Index Event Status bit
| Value | Description |
|---|---|
1 | Index event has occurred |
0 | No index event has occurred |
Bit 0 – IDXIEN Index Input Event Interrupt Enable bit
| Value | Description |
|---|---|
1 | Index input event interrupt is enabled |
0 | Index input event interrupt is disabled |