20.3.1 QEI Control Register
- When CCMx =
10or CCMx =11, all of the QEI counters operate as timers and the PIMOD[2:0] bits are ignored. - When CCMx =
00, and QEAx and QEBx values match the Index Match Value (IMV), the POSxCNT registers are reset. - The selected clock rate should be at least twice the expected maximum quadrature count rate.
- The index match value applies to the A and B inputs after the SWAP, and polarity bits have been applied.
- The QCAPEN and HCAPEN bits must be cleared during PIMODx Modes two through seven to ensure proper functionality.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | QEI1CON |
| Offset: | 0x1A00 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | PIMOD[2:0] | IMV[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INTDIV[2:0] | CNTPOL | GATEN | CCM[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – ON Quadrature Encoder Interface Module Counter Enable bit
| Value | Description |
|---|---|
1 | Module counters are enabled |
0 | Module counters are disabled, but SFRs can be read or written |
Bit 13 – SIDL QEI Stop in Idle Mode bit
| Value | Description |
|---|---|
1 | Discontinues module operation when device enters Idle mode |
0 | Continues module operation in Idle mode |
Bits 12:10 – PIMOD[2:0] Position Counter Initialization Mode Select bits(1,5)
| Value | Description |
|---|---|
111 | Modulo Count mode for Position Counter and every index event resets the position counter |
110 | Modulo Count mode for Position Counter |
101 | Resets the position counter when the Position Counter equals the QEIxGEC register |
100 | Second index event after home event initializes the Position Counter with the contents of the QEIxIC register |
011 | First index event after home event initializes the Position Counter with the contents of the QEIxIC register |
010 | Next index input event initializes the Position Counter with the contents of the QEIxIC register |
001 | Every index input event resets the Position Counter |
000 | Index input event does not affect the Position Counter |
Bits 9:8 – IMV[1:0] Index Match Value bits(2,4)
| Value | Description |
|---|---|
11 | Index match occurs when QEBx = |
10 | Index match occurs when QEBx = |
01 | Index match occurs when QEBx = |
00 | Index match occurs when QEBx = |
Bits 6:4 – INTDIV[2:0] Timer Input Clock Prescale Select bits(3)
| Value | Description |
|---|---|
111 | 1:128 prescale value |
110 | 1:64 prescale value |
101 | 1:32 prescale value |
100 | 1:16 prescale value |
011 | 1:8 prescale value |
010 | 1:4 prescale value |
001 | 1:2 prescale value |
000 | 1:1 prescale value |
Bit 3 – CNTPOL Position and Index Counter/Timer Direction Select bit
| Value | Description |
|---|---|
1 | Counter direction is negative unless modified by an external up/down signal |
0 | Counter direction is positive unless modified by an external up/down signal |
Bit 2 – GATEN External Count Gate Enable bit
| Value | Description |
|---|---|
1 | External gate signal controls Position Counter operation |
0 | External gate signal does not affect Position Counter operation |
Bits 1:0 – CCM[1:0] Counter Control Mode Selection bits
| Value | Description |
|---|---|
11 | Internal Timer mode |
10 | External clock count with External Gate mode |
01 | External clock count with External Up/Down mode |
00 | Quadrature Encoder mode |