This provides a delay between
writing to the transmit buffer and releasing the SCL by hardware; it is used for
the release of SCL by hardware.
In Smart mode, the SDA set up
timer is used by hardware to release SCL.
Table 23-18. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
I2CxSDASUT
Offset:
0x18C0,
0x1910
Bit
31
30
29
28
27
26
25
24
SDASUTEN
Access
R/W
Reset
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
SDASUT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SDASUT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 31 – SDASUTEN
I2C Bus SDA-to-SCL Set-up Time Enable bit
Bits 15:0 – SDASUT[15:0]
I2C Bus SDA-to-SCL Set-up Time Timer bits
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
