23.4.8 I2Cx Control Register
- Automatically cleared to
‘
0’ at the beginning of client transmission; automatically cleared to ‘0’ at the end of client reception. - Automatically cleared to
‘
0’ at the beginning of client transmission. - When EPSZE is enabled, Smart mode (SMEN=1), clock stretching (STREN=1) and EOP
function (EOPSC= “
10” or “01” should be enabled. - In Host mode , when ACKC !=
00, hardware will automatically set ACKEN (I2CxCON1[4]) bit. - In Host mode, this bit will be used by PSZ(I2CxCON2[15:0]) to count the data bytes.
- In Client mode, this bit is used
for TX/RX interrupt generation.
If ‘
1’, Interrupt is generated only for data bytes. If ‘0’, Interrupt is generated for both address and data bytes. - In Client mode, it should set the ND/A to ‘1’ before enabling transfers through DMA for data transfer.
- The packet size should be excluding of address byte(s). It should not be changed on fly and should be changed when the bus is in Idle state.
- In Host mode, the EOPSC and ND/A bit control the PSZ to decrement.
- For the host, the software has to
clear the CRC calculator by setting I2CxCON2.PECC to “
11” for new data frame transaction. - To use the Auto-Append mode, the PECC needs to be set to “
01” at least one data byte earlier than the CRC byte of data.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | I2CxCON2 |
| Offset: | 0x189C, 0x18EC |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AMODE[1:0] | PECC[1:0] | BSCLTE | HBCTE | CBCTE | EPSZE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ACKC[1:0] | HNACKIGN | EOPSC[1:0] | ND/A | SMEN | BITE | ||||
| Access | R/W | R/W | R/W | R/W/HC | R/W/HC | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PSZ[15:0] | |||||||||
| Access | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PSZ[15:0] | |||||||||
| Access | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 31:30 – AMODE[1:0] Address Mode bit
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | The client responds to the range of addresses between and including I2CxADD and I2CxMSK. I2CxMSK is the upper limit |
| 01 | The client responds to the two unique addresses in I2CxADD and I2CxMSK |
| 00 | I2CxMSK is used as a mask to the I2CxADD register |
Bits 29:28 – PECC[1:0] PEC Control bit(10,11)
| Value | Description |
|---|---|
| 11 | PEC reset |
| 10 | PEC append
is disabled. CRC-8 calculator will be active. On a read request (receive), calculated CRC-8 is copied into CCRC (I2CxPEC[15:8]) at EOP. On a write request (transmit), calculated CRC-8 is copied into CCRC (I2CxPEC[15:8]) at EOP. |
| 01 |
Calculated CRC-8 is appended at the end of a packet. On a read request (receive), calculated CRC-8 is copied into CCRC (I2CxPEC[15:8]) and received CRC will be copied into RCRC (I2CxPEC[7:0]) at EOP. On a write Request (transmit), calculated CRC-8 will be automatically appended and also copied into CCRC (I2CxPEC[15:8]) at the end of the data transmission. PEC will be get reset after appending. |
| 00 | PEC disabled |
Bit 27 – BSCLTE Bus SCL Time-out Enable bit
| Value | Description |
|---|---|
1 | SCL low time-out enabled |
0 | SCL low time-out disabled |
Bit 26 – HBCTE Host Bus SCL Cumulative (Extended time) Low Time-out Enable bit
| Value | Description |
|---|---|
1 | SCL Cumulative low extended time-out enable |
0 | SCL Cumulative low extended time-out disable |
Bit 25 – CBCTE Client Bus SCL Cumulative (Extended time) Low Time-out Enable bit
| Value | Description |
|---|---|
1 | SCL Cumulative low extended time-out enable |
0 | SCL Cumulative low extended time-out disable |
Bit 24 – EPSZE Extended Packet Size Enable bit (Valid for Client Receive mode only)(3)
| Value | Description |
|---|---|
1 | Extended packet size enabled after EOP=1 |
0 | Extended packet size disable |
Bits 23:22 – ACKC[1:0] ACK Control bit(4)
| Value | Description |
|---|---|
| 11 |
Host: ACK all the bytes except the CRC byte; for the CRC byte, NACK will be sent Client: ACK all the bytes and for the last byte, which is the CRC byte, ACK or
NACK based on CRC result
|
| 10 | ACK all the bytes and the last byte will be NACKed (to be used only for last packet) |
| 01 | ACK all bytes including end of packet (to be used for extended packets) |
| 00 |
ACK/NACK based on ACKDT and BOEN (client) ACK/NACK based on ACKEN and ACKDT (host) |
Bit 21 – HNACKIGN Host NACK Response Ignore Control bit
| Value | Description |
|---|---|
| 1 | Host treats all NACK responses as ACK |
0 | Normal operation; host treats NACK responses as NACK only |
Bits 20:19 – EOPSC[1:0] End of Packet Status Control bit
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | I2CxSTAT2.EOP will be set after data bytes and PEC |
| 01 | I2CxSTAT2.EOP will be set after data bytes |
| 00 | End of packet function is disabled |
Bit 18 – ND/A Next Data/Address Byte Transmission bit(5,6,7)
| Value | Description |
|---|---|
1 | Next transmission is a data byte transmission |
0 | Next transmission is an address byte transmission |
Bit 17 – SMEN Smart Mode Enable bit
| Value | Description |
|---|---|
1 | Smart mode is enable |
0 | Smart mode is disabled |
Bit 16 – BITE Bus Idle Time-out Enable bit
| Value | Description |
|---|---|
1 | Bus idle time-out enable |
0 | Bus idle time-out disabled |