The following
configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Name:
LCDC_HEOIER
Offset:
0x0000034C
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
VOVR
VDONE
VADD
VDSCR
VDMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
15
14
13
12
11
10
9
8
UOVR
UDONE
UADD
UDSCR
UDMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
OVR
DONE
ADD
DSCR
DMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 22 – VOVR Overflow for V Chrominance Interrupt
Enable
Bit 21 – VDONE End of List for V Chrominance Interrupt
Enable
Bit 20 – VADD Head Descriptor Loaded for V Chrominance Interrupt
Enable
Bit 19 – VDSCR Descriptor Loaded for V Chrominance Interrupt
Enable
Bit 18 – VDMA End of DMA for V Chrominance Transfer Interrupt
Enable
Bit 14 – UOVR Overflow for U or UV Chrominance Interrupt
Enable
Bit 13 – UDONE End of List for U or UV Chrominance Interrupt
Enable
Bit 12 – UADD Head Descriptor Loaded for U or UV Chrominance
Interrupt Enable
Bit 11 – UDSCR Descriptor Loaded for U or UV Chrominance Interrupt
Enable
Bit 10 – UDMA End of DMA Transfer for U or UV Chrominance
Interrupt Enable
Bit 6 – OVR Overflow Interrupt
Enable
Bit 5 – DONE End of List Interrupt
Enable
Bit 4 – ADD Head Descriptor Loaded Interrupt
Enable
Bit 3 – DSCR Descriptor Loaded Interrupt
Enable
Bit 2 – DMA End of DMA Transfer Interrupt
Enable
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