38.7.1 LCD Controller Configuration Register 0
Name: | LCDC_LCDCFG0 |
Offset: | 0x00 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CLKDIV[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CGDISPP | CGDISHEO | CGDISOVR2 | CGDISOVR1 | CGDISBASE | |||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CLKPWMSEL | CLKSEL | CLKPOL | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bits 23:16 – CLKDIV[7:0] LCD Controller Clock Divider
8-bit width clock divider for pixel clock (LCDPCLK). The pixel clock period formula is:
LCDPCLK = source clock / (CLKDIV+2)
where source clock is the system clock when CLKSEL is written to ‘0’, and 2x system_clock when CLKSEL is written to ‘1’.
Bit 13 – CGDISPP Clock Gating Disable Control for the Post Processing Layer
Value | Description |
---|---|
0 |
Automatic Clock Gating is enabled for the Post Processing Layer. |
1 |
Clock is running continuously. |
Bit 11 – CGDISHEO Clock Gating Disable Control for the High-End Overlay
Value | Description |
---|---|
0 |
Automatic Clock Gating is enabled for the High-End Overlay Layer. |
1 |
Clock is running continuously. |
Bit 10 – CGDISOVR2 Clock Gating Disable Control for the Overlay 2 Layer
Value | Description |
---|---|
0 |
Automatic Clock Gating is enabled for the Overlay 2 Layer. |
1 |
Clock is running continuously. |
Bit 9 – CGDISOVR1 Clock Gating Disable Control for the Overlay 1 Layer
Value | Description |
---|---|
0 |
Automatic Clock Gating is enabled for the Overlay 1 Layer. |
1 |
Clock is running continuously. |
Bit 8 – CGDISBASE Clock Gating Disable Control for the Base Layer
Value | Description |
---|---|
0 | Automatic Clock Gating is enabled for the Base Layer. |
1 | Clock is running continuously. |
Bit 3 – CLKPWMSEL LCD Controller PWM Clock Source Selection
Value | Description |
---|---|
0 | The slow clock is selected and feeds the PWM module. |
1 | The system clock is selected and feeds the PWM module. |
Bit 2 – CLKSEL LCD Controller Clock Source Selection
Value | Description |
---|---|
0 | The asynchronous output stage of the LCD controller is fed by the System Clock. |
1 | The asynchronous output state of the LCD controller is fed by the 2x System Clock. |
Bit 0 – CLKPOL LCD Controller Clock Polarity
Value | Description |
---|---|
0 | Data/Control signals are launched on the rising edge of the pixel clock. |
1 | Data/Control signals are launched on the falling edge of the pixel clock. |