38.7.6 LCD Controller Configuration Register 5
Name: | LCDC_LCDCFG5 |
Offset: | 0x14 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
GUARDTIME[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
VSPHO | VSPSU | PP | MODE[1:0] | ||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DISPDLY | DITHER | DISPPOL | VSPDLYE | VSPDLYS | VSPOL | HSPOL | |||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:16 – GUARDTIME[7:0] LCD DISPLAY Guard Time
Number of frames inserted during startup before LCDDISP assertion.
Number of frames inserted after LCDDISP reset.
Bit 13 – VSPHO LCD Controller Vertical synchronization Pulse Hold Configuration
Value | Description |
---|---|
0 | The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. |
1 | The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse. |
Bit 12 – VSPSU LCD Controller Vertical synchronization Pulse Setup Configuration
Value | Description |
---|---|
0 | The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. |
1 | The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse. |
Bit 10 – PP Post Processing Enable
Value | Description |
---|---|
0 | The blended pixel is pushed into the output FIFO. |
1 | The blended pixel is written back to memory, the post-processing stage is enabled. |
Bits 9:8 – MODE[1:0] LCD Controller Output Mode
Value | Name | Description |
---|---|---|
0 | OUTPUT_12BPP | LCD Output mode is set to 12 bits per pixel |
1 | OUTPUT_16BPP | LCD Output mode is set to 16 bits per pixel |
2 | OUTPUT_18BPP | LCD Output mode is set to 18 bits per pixel |
3 | OUTPUT_24BPP | LCD Output mode is set to 24 bits per pixel |
Bit 7 – DISPDLY LCD Controller Display Power Signal Synchronization
Value | Description |
---|---|
0 | The LCDDISP signal is asserted synchronously with the second active edge of the horizontal pulse. |
1 | The LCDDISP signal is asserted asynchronously with both edges of the horizontal pulse. |
Bit 6 – DITHER LCD Controller Dithering
Value | Description |
---|---|
0 | Dithering logical unit is disabled |
1 | Dithering logical unit is activated |
Bit 4 – DISPPOL Display Signal Polarity
Value | Description |
---|---|
0 | Active High |
1 | Active Low |
Bit 3 – VSPDLYE Vertical Synchronization Pulse End
Value | Description |
---|---|
0 | The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. |
1 | The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. |
Bit 2 – VSPDLYS Vertical Synchronization Pulse Start
Value | Description |
---|---|
0 | The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. |
1 | The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. |
Bit 1 – VSPOL Vertical Synchronization Pulse Polarity
Value | Description |
---|---|
0 | Active High |
1 | Active Low |
Bit 0 – HSPOL Horizontal Synchronization Pulse Polarity
Value | Description |
---|---|
0 | Active High |
1 | Active Low |