10.2.2.2 IGLOO® and ProASIC® 3 Dynamic CCC I/O Description
The following table lists the I/O description of a IGLOO and ProASIC3 Dynamic CCC .
| Name | Size | Type | Required/ Optional | Function |
|---|---|---|---|---|
| GLA | 1 | Output | Required | Primary clock output |
| CLKA | 1 | Input | Required | Reference clock |
| POWERDOWN | 1 | Input | Required | Power Down Signal. A low on this signal turns off the Dynamic CCC |
| LOCK | 1 | Output | Required | Dynamic CCC lock |
| SDOUT | 1 | Output | Required | Serial interface shift register output |
| SCLK | 1 | Input | Required | Shift clock |
| SSHIFT | 1 | Input | Optional | Serial Shift enable |
| SDIN | 1 | Input | Optional | Serial Data in for Dynamic CCC configuration bits |
| SUPDATE | 1 | Input | Optional | Serial update |
| MODE | 1 | Input | Optional | Dynamic or Static mode indicator. A Low on this signal indicates static mode and a High indicates dynamic. |
| EXTFB | 1 | Input | Optional | External feedback |
| CLKB | 1 | Input | Optional | Input clock for Secondary 1 clock; valid only in bypass mode. |
| GLB | 1 | Output | Optional | Global Output for Secondary1 Clock |
| YB | 1 | Output | Optional | Core Output for Secondary1 Clock |
| CLKC | 1 | Input | Optional | Input clock for Secondary 2 clock.; valid only in bypass mode. |
| GLC | 1 | Output | Optional | Global Output for Secondary2 Clock |
| YC | 1 | Output | Optional | Core Output for Secondary2 Clock |
