10.2.2.1.1 Configuring Control Bits in the Dynamic CCC
The software prints out all the values of the configuration pins in a report. You can use these to specify the bitstream that can be shifted in through the shift register.
You can use the “control bits” to select the ratios used in the various dividers, the signals selected by the multiplexors and “power-down” control for the CCC block. The signals applied to the control inputs can come from one of two sources:
- Flash configuration bits set by the software or by you. These bits are set in the bitstream file and provide the default state and mode of the PLL core.
- Synchronous serial interface with access to and from the logic core. This method is very powerful, because it allows core driven dynamic PLL reconfiguration. The reconfiguration does not unlock the PLL as long as it does not change the state of the input divider or feedback elements. (This interface also includes an asynchronous “update” latch for the configuration inputs to the multiplexer). SUPDATE must be low during any clock cycle where SSHIFT is active.
A total of 81 configuration bits must be specified to change the configuration. When you use the software to define the configuration that is shifted-in through the serial interface, it prints out the values of the 81 configuration bits.
The combiner infers STATASEL, STATBSEL, STATCSEL.DYNASEL, DYNBSEL, DYNCSEL and RESET_ENABLE.
To enter a new configuration, all 81 bits must shift through SDIN. After all bits are shifted, SSHIFT must go low and SUPDATE high, to enable the new configuration. For simulation purposes, bits <71:73> and <77:79> are don't cares. The core configurator software defines 74 bits. Six more bits are not available until after layout and are defined in the post-layout report. The last bit is RESETENABLE; it is always 1.
The following table defines all the configuration bits required to enter a new configuration.
| NAME | FUNCTION |
|---|---|
| FINDIV<6:0> | 7-BIT INPUT DIVIDER (/N) |
| FBDIV<6:0> | 7-BIT FEEDBACK DIVIDER (/M) |
| OADIV<4:0> | 5-BIT OUTPUT DIVIDER (/U) |
| OBDIV<4:0> | 5-BIT OUTPUT DIVIDER (/V) |
| OCDIV<4:0> | 5-BIT OUTPUT DIVIDER (/W) |
| OAMUX<2:0> | 3-BIT POST-PLL MUXA (BEFORE DIVIDER /U) |
| OBMUX<2:0> | 3-BIT POST-PLL MUXB (BEFORE DIVIDER /V) |
| OCMUX<2:0> | 3-BIT POST-PLL MUXC (BEFORE DIVIDER /W) |
| FBSEL<1:0> | 2-BIT PLL FEEDBACK MUX |
| FBDLY<4:0> | FEEDBACK DELAY |
| XDLYSEL | 1-BIT PLL FEEDBACK MUX |
| DLYHCA<4:0> | DELAY ON GLOBAL A |
| DLYHCB<4:0> | DELAY ON GLOBAL B |
| DLYHCC<4:0> | DELAY ON GLOBAL C |
| DLYB<4:0> | DELAY ON YB |
| DLYC<4:0> | DELAY ON YC |
| STATASEL | MUX SELECT ON INPUT A |
| STATBSEL | MUX SELECT ON INPUT B |
| STATCSEL | MUX SELECT ON INPUT C |
| VCOSEL<2:0> | 3-BIT VCO GEAR CONTROL (4 FREQUENCY RANGES) |
| DYNASEL | DYNAMIC SELECT ON INPUT B |
| DYNBSEL | DYNAMIC SELECT ON INPUT A |
| DYNCSEL | DYNAMIC SELECT ON INPUT C |
| RESET_ENABLE |