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21
SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.15.11
set_load
21.15.11.2
Supported Families
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18
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.15.1
About Synopsys Design Constraints (SDC) Files
21.15.2
SDC Syntax Conventions
21.15.3
create_clock
21.15.4
create_generated_clock
21.15.5
remove_clock_uncertainty
21.15.6
set_clock_latency
21.15.7
set_clock_uncertainty
21.15.8
set_disable_timing
21.15.9
set_false_path
21.15.10
set_input_delay
21.15.11
set_load
21.15.11.1
Arguments
21.15.11.2
Supported Families
21.15.11.3
Description
21.15.11.4
Examples
21.15.11.5
Microchip Implementation Specifics
21.15.12
set_max_delay (SDC)
21.15.13
set_min_delay
21.15.14
set_multicycle_path
21.15.15
set_output_delay
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.15.11.2 Supported Families
IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A
Rev: A
