8.6.13 Using FPGA Express with SpeedWave

When using FPGA Express with SpeedWave, you do not need to use ViewDraw, ViewSim, ViewGen, or Innoveda EDIF interfaces. You use three point tools: SpeedWave, FPGA Express, and Designer.

1. Synthesize your design in FPGA Express. Create or open an existing FPGA Express project. Add your VHDL source file(s) to the project.
2. In the Create Implementation dialog box, be sure that the “Do not insert I/O pads” checkbox is not selected.
3. In the Export dialog box, select “%s<%d:%d>” for Bus Style and NONE for the Simulation Output Format. An EDIF netlist is exported by FPGA Express.