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8
Innoveda eProduct Designer Interface Guide – Windows
8.6
Actel-Innoveda Design Considerations
8.6.4
Buried I/Os
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
8
Introduction
8.1
About this Document
8.2
Setup
8.3
User Setup
8.4
Project Setup
8.5
Actel-Innoveda Design Flow
8.6
Actel-Innoveda Design Considerations
8.6.1
Naming Conventions
8.6.2
Adding Pins to the Schematic
8.6.3
Generating a Top-Level Symbol
8.6.4
Buried I/Os
8.6.5
Adding Power and Ground
8.6.6
Sheets and Symbols
8.6.7
Assigning Pins in a Schematic
8.6.8
Adding SmartGen Cores
8.6.9
Adding IP cores in a Schematic
8.6.10
Adding FPGA Express Blocks
8.6.11
Generating an EDIF Netlist
8.6.12
Generating a Structural VHDL Netlist
8.6.13
Using FPGA Express with SpeedWave
8.6.14
Using FPGA Express with ViewSim
8.7
Simulation Using ViewSim
8.8
Simulation Using SpeedWave
8.9
Revision History
8
Microchip FPGA Support
8
Microchip Information
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
8.6.4 Buried I/Os
I/O cores can be buried in the design hierarchy.
Rev: A
