8.6.14 Using FPGA Express with ViewSim

When using FPGA Express with ViewSim, you cannot perform a behavioral simulation. You need to import the synthesized design into the ViewDraw/ViewSim environment.

1. Synthesize your design in FPGA Express. Create or open an existing FPGA Express project. Add your VHDL source file(s) to the project.
2. In the Create Implementation form, make sure that the “Do not insert I/O pads” checkbox is not selected.
3. In the Export dialog box, select “%s<%d:%d>” for Bus Style and NONE for the Simulation Output Format. FPGA Express exports an EDIF netlist.
4. Import the synthesized EDIF into the ViewDraw/ViewSim environment. Invoke the EDIF Interfaces program and select the EDIF Netlist Reader tab. Specify the EDIF file created by FPGA Express as the Input and your Innoveda project directory as your Output Dir.