8.6.9 Adding IP cores in a Schematic

VHDL or Verilog cores can be added to the schematic design, without generating any schematics for the core. The following steps describe the procedure.

  1. Generate both EDIF and VHDL netlist for the core using the synthesis tool.
  2. Invoke EDIF Interface tool.
  3. Generate wire files for the core using EDIF netlist reader option in the EDIF interface tool.
  4. Invoke Viewgen.
  5. Generate top-level symbol for the core using Viewgen tool.
  6. Invoke Viewdraw.
  7. Add the core as a component in the schematic. Add the top-level symbol of the design. Refer to the Innoveda documentation for information about adding the components to a schematic.
  8. Add attributes to the core. Double click on the component, Component properties dialog box appears, as shown in Figure 8-1.
  9. Click Attributes tab of the dialog box.
  10. Set the following three attributes for this component. LEVEL: Set this attribute value to VHDL, as core used in this example is a VHDL core. VHDL: Set this value to top level entity name. VHDL_FILE: Set this attribute to, path to the VHD file for the core.
  11. Enter Attributes name in the Name field.
  12. Enter Attributes value in the Value field.
  13. Click set to add the attributes.
  14. Click OK to dismiss the properties dialog box.
  15. Save check the schematic.
  16. Generate EDIF netlist for this schematic. Follow the method shown in “Generating an EDIF Netlist .
  17. Import this netlist into designer.