8.6.10 Adding FPGA Express Blocks

FPGA Express can generate blocks that can be added to your ViewDraw schematic. The following steps describe the procedure.

  1. Invoke FPGA Express.
  2. Create a new project or open an existing one. Add your VHDL source file(s) to the project.
  3. Create an implementation. In the Create Implementation form, select “Do not insert I/O pads.”
  4. Export the Netlist. In the Export form, select “%s<%d:%d>” for Bus Style and NONE for the Simulation Output Format.
  5. Save the Project and exit FPGA Express.
  6. Translate the EDIF file into ViewDraw’s wir format. Invoke the EDIF Interfaces program and select the EDIF Netlist Reader tab. Specify the EDIF file created by FPGA Express as the Input and your Innoveda project directory as your Output Dir.
  7. Invoke ViewGen to generate a symbol. Specify the .wir file generated by the EDIF Netlist Reader as the input. Select “Generate the top level symbol” and optionally, “Generate schematic.”
  8. Add the symbol to your ViewDraw schematic. For information about adding symbols to a schematic, see to the Innoveda documentation.

For more information, see the FPGA Express and other eProduct Designer online help.