8.6.12 Generating a Structural VHDL Netlist

You can generate a structural VHDL netlist for SpeedWave simulation from your EDIF netlist by either exporting it from Designer or by using the “edn2vhdl” program. The structural VHDL netlist generated by Designer and the “edn2vhdl” use std_logic for all ports. The bus ports are in the same bit order as they appear in the EDIF netlist.

To generate a structural VHDL netlist using Designer, perform these steps:

  1. Invoke Designer.
  2. Import the EDIF netlist. Select the Import Netlist File command from the File menu. The Import Netlist dialog box is displayed. Specify EDIF as the Netlist Type, GENERIC (or INNOVEDA if you are using an Innoveda synthesis tool) as the Edif Flavor. Type the full path name of your EDIF netlist or use the Browse button to select your design. Click OK.
  3. Export the structural VHDL netlist. Select the Export command from the File menu. The Export dialog box is displayed. Specify Netlist File as the File Type and VHDL as the Format. Click OK.

To generate a structural VHDL netlist using edn2vhdl, perform these steps:‘

  1. Open a DOS window.
  2. Change to the directory that contains the EDIF netlist.
  3. Translate the EDIF netlist to a structural VHDL Netlist. Type the following command at the prompt:

    edn2vhdl fam:<act_fam> <design_name>