14.11.8 DDR Macro
DDR_REG macro
This component is supported by Accelerator families.
- Function: DDR (DDR) Register with active-low write and read enables.
- Input: D, CLK, E, PRE, CLR
- Output: QR, QF
| CLR | PRE | E | CLK | QR(n+1) | QF(n+1) |
|---|---|---|---|---|---|
| 0 | X | X | X | 0 | 0 |
| 1 | 0 | X | X | 1 | 1 |
| 1 | 1 | 1 | X | QR(n) | QF(n) |
| 1 | 1 | 0 | ↑ | D(↑) | X |
| 1 | 1 | 0 | ↓ | X | D(↓) |
SIMBUF
This component is supported by Accelerator families.
- Function: SIMBUF is a VIRTUAL I/O used to bring out internal nets that are going to be connected to a top port in the design. This port will be used exclusively for simulation. This virtual I/O is removed by Designer during compile, then re-added in the back-annotated netlist.
- Input: D
- Output: PAD
| D | PAD |
|---|---|
| 0 | 0 |
| 1 | 1 |