14.11.4 HClock Buffers

Naming convention is identical to the naming for Clock Buffers.

HCLKBUF_X

This component is supported by Accelerator families.

Figure 14-501. HCLKBUF_X Logic Diagram
  • Function: Dedicated high-speed S-Module Clock Buffer
  • Input: PAD
  • Output: Y
Table 14-920. Truth Table
PADY
00
11
Table 14-921. Truth Table
FamilySeqI/O
All—1
Table 14-922. Available HCLKBUF_X Macro Types
NameDescription
HCLKBUF_LVCMOS25LVCMOS Clock buffer with 2.5 CMOS voltage level
HCLKBUF_LVCMOS18LVCMOS Clock buffer with 1.8 CMOS voltage level
HCLKBUF_LVCMOS15LVCMOS Clock buffer with 1.5 CMOS voltage level
HCLKBUF_PCIPCI Clock buffer
HCLKBUF_PCIXPCIX Clock buffer
HCLKBUF_GTLP25GTLP Clock buffer with 2.5 CMOS voltage level
HCLKBUF_GTLP33GTLP Clock buffer with 3.3 CMOS voltage level
HCLKBUF_ HSTL _IHSTL Class I Clock buffer
HCLKBUF_SSTL2_ISSTL2 Class I Clock buffer
HCLKBUF_SSTL2_IISSTL2 Class II Clock buffer
HCLKBUF_SSTL3_ISSTL3 Class I Clock buffer
HCLKBUF_SSTL3_IISSTL3 Class II Clock buffer