21.14.7.4 Examples

The following example creates a generated clock on pin U1/reg1:Q with a period twice as long as the period at the reference port CLK.

create_generated_clock -name {my_user_clock} –divide_by 2 –source [get_ports {CLK}] U1/reg1:Q

The following example creates a generated clock at the primary output of myPLL with a period ¾ of the period at the reference pin clk.

create_generated_clock –divide_by 3 –multiply_by 4 -source clk [get_pins {myPLL:CLK1}]