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Libero IDE v9.x
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13
Libero IDE
13.29
Running Layout
13.29.33
Report (Global Usage)
13.29.33.3
Exceptions
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
13
What's New in Libero IDE v9.1
13.1
Supported Families
13.2
Project Management
13.3
Project Files
13.4
Project Options
13.5
Settings
13.6
Preferences
13.7
Project Manager Interface
13.8
Designing with Designer Block Components
13.9
Creating a Designer Block Component in Libero IDE
13.10
Creating a Designer Block Component in Designer
13.11
Instantiating a Designer Block Component in Designer
13.12
SmartDesign
13.13
Getting Started with SmartDesign
13.14
SmartDesign User Interface
13.15
Canvas View
13.16
Grid
13.17
Instance-Instance View
13.18
Schematic View
13.19
Creating a SmartDesign
13.20
Connecting Instances
13.21
Bus Interfaces
13.22
Incremental Design
13.23
Reference
13.24
Welcome to Designer
13.25
Device Selection
13.26
Design Constraints
13.27
Families Supported
13.28
Entering Constraints
13.29
Running Layout
13.29.1
IGLOO, ProASIC3, SmartFusion and Fusion Layout Options
13.29.2
IGLOO, ProASIC3, SmartFusion and Fusion Advanced Layout Options
13.29.3
ProASIC
PLUS
and ProASIC Layout Options
13.29.4
ProASIC
PLUS
and ProASIC Advanced Layout Options
13.29.5
Axcelerator Layout Options
13.29.6
Axcelerator Advanced Layout Options
13.29.7
eX, SX, SX-A Layout Options
13.29.8
eX, SX, and SX-A Advanced Layout Options
13.29.9
ACT, MX, and DX Layout Options
13.29.10
ACT, MX, and DX Advanced Layout Options
13.29.11
Incremental Placement
13.29.12
Running Multiple Pass Layout
13.29.13
Analyzing timing in your design
13.29.14
Analyzing power consumption in your design
13.29.15
Viewing your netlist
13.29.16
Back-Annotation
13.29.17
Report types
13.29.18
Status Reports
13.29.19
Generating a Timing Report
13.29.20
Generating a Timing Violation Report
13.29.21
Generating a Bottleneck Report
13.29.22
Generating a Datasheet Report
13.29.23
Generating a Constraints Coverage Report
13.29.24
Generating a Combinational Loop Report
13.29.25
Pin reports
13.29.26
Flip-flop reports
13.29.27
I/O Bank Reports
13.29.28
Power Reports
13.29.29
Cycle-Accurate Power Reports
13.29.30
Activity and Hazards Reports
13.29.31
Scenario Power Report
13.29.32
CCC Configuration report
13.29.33
Report (Global Usage)
13.29.33.1
Arguments
13.29.33.2
Supported Families
13.29.33.3
Exceptions
13.29.33.4
Examples
13.29.34
Global Usage Report
13.29.35
Designer Block Report
13.29.36
Compile Report
13.30
Device Programming
13.31
Generating Programming Files
13.32
TCL Command Reference
13.33
Project Manager Tcl Commands
13.34
Reference
13.35
Dialog Boxes
13.36
Revision History
13
Microchip FPGA Support
13
Microchip Information
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
13.29.33.3 Exceptions
None
Rev: A
