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Libero IDE v9.x
Libero IDE v9.x
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  2. 21 SmartTime
  3. 21.14 Data Change History – SmartTime
  4. 21.14.1 all_inputs
  5. 21.14.1.3 Exceptions
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  • 21 SmartTime
    • 21 Introduction
    • 21.1 Design Flows with SmartTime
    • 21.2 Starting and Closing SmartTime
    • 21.3 SmartTime Components
    • 21.4 SmartTime Constraint Scenario
    • 21.5 Setting SmartTime Options
    • 21.6 SmartTime Tutorial
    • 21.7 SmartTime Constraints Editor
    • 21.8 SmartTime Timing Analyzer
    • 21.9 Advanced Timing Analysis
    • 21.10 Generating Timing Reports
    • 21.11 Timing Concepts
    • 21.12 Dialog Boxes
    • 21.13 Menus, Tools, and Shortcut Keys
    • 21.14 Data Change History – SmartTime
      • 21.14.1 all_inputs
        • 21.14.1.1 Arguments
        • 21.14.1.2 Supported Families
        • 21.14.1.3 Exceptions
        • 21.14.1.4 Examples
      • 21.14.2 all_outputs
      • 21.14.3 all_registers
      • 21.14.4 check_timing_constraints
      • 21.14.5 clone_scenario
      • 21.14.6 create_clock
      • 21.14.7 create_generated_clock
      • 21.14.8 create_scenario
      • 21.14.9 delete_scenario
      • 21.14.10 get_cells
      • 21.14.11 get_clocks
      • 21.14.12 get_current_scenario
      • 21.14.13 get_nets
      • 21.14.14 get_pins
      • 21.14.15 get_ports
      • 21.14.16 list_clock_uncertainties
      • 21.14.17 list_disable_timings
      • 21.14.18 list_objects
      • 21.14.19 list_scenarios
      • 21.14.20 remove_clock
      • 21.14.21 remove_clock_latency
      • 21.14.22 remove_clock_uncertainty
      • 21.14.23 remove_disable_timing
      • 21.14.24 remove_false_path
      • 21.14.25 remove_generated_clock
      • 21.14.26 remove_input_delay
      • 21.14.27 remove_max_delay
      • 21.14.28 remove_min_delay
      • 21.14.29 remove_multicycle_path
      • 21.14.30 remove_output_delay
      • 21.14.31 rename_scenario
      • 21.14.32 set_clock_latency
      • 21.14.33 set_clock_uncertainty
      • 21.14.34 set_current_scenario
      • 21.14.35 set_disable_timing
      • 21.14.36 set_false_path (GCF)
      • 21.14.37 set_input_delay
      • 21.14.38 set_max_delay
      • 21.14.39 set_min_delay
      • 21.14.40 set_multicycle_path
      • 21.14.41 set_output_delay
      • 21.14.42 st_commit
      • 21.14.43 st_create_set
      • 21.14.44 st_edit_set
      • 21.14.45 st_expand_path
      • 21.14.46 st_list_paths
      • 21.14.47 st_remove_set
      • 21.14.48 st_restore
      • 21.14.49 st_set_options
      • 21.14.50 timer_add_clock_exception
      • 21.14.51 timer_add_pass
      • 21.14.52 timer_add_stop
      • 21.14.53 timer_commit
      • 21.14.54 timer_get_clock_actuals
      • 21.14.55 timer_get_clock_constraints
      • 21.14.56 timer_get_maxdelay
      • 21.14.57 timer_get_path
      • 21.14.58 timer_get_path_constraints
      • 21.14.59 timer_remove_all_constraints
      • 21.14.60 timer_remove_clock_exception
      • 21.14.61 timer_remove_pass
      • 21.14.62 timer_remove_stop
      • 21.14.63 timer_restore
      • 21.14.64 timer_set_maxdelay
      • 21.14.65 timer_setenv_clock_freq
      • 21.14.66 timer_setenv_clock_period
      • 21.14.67 report (Timing) using SmartTime
      • 21.14.68 report (Timing violations) using SmartTime
      • 21.14.69 report (Datasheet) using SmartTime
      • 21.14.70 report (Bottleneck) using SmartTime
    • 21.15 Constraints by File Format - SDC Command Reference
    • 21.16 Design Object Access Commands
    • 21.17 Glossary
    • 21.18 Revision History
    • 21 Microchip FPGA Support
    • 21 Microchip Information
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

21.14.1.3 Exceptions

You can only use this command as part of a –from, -to, or –through argument in the following Tcl commands: set_min_delay ,set_max_delay , set_multicycle_path and set_false_path.

Rev: A

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