20.3.1 SENTx Control Register 1
- This bit has no function in Receive mode (RCVEN =
1). - This bit has no function in Transmit mode (RCVEN =
0).
| Name: | SENTxCON1 |
| Offset: | 0x080, 0x084, 0x088 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SNTEN | SNTSIDL | RCVEN | TXM | TXPOL | CRCEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PPP | SPCEN | PS | NIBCNT[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – SNTEN SENTx Enable bit
| Value | Description |
|---|---|
1 |
SENTx is enabled |
0 |
SENTx is disabled |
Bit 13 – SNTSIDL SENTx Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues module operation when the device enters Idle mode |
0 |
Continues module operation in Idle mode |
Bit 11 – RCVEN SENTx Receive Enable bit
| Value | Description |
|---|---|
1 |
SENTx operates as a receiver |
0 |
SENTx operates as a transmitter (sensor) |
Bit 10 – TXM SENTx Transmit Mode bit(1)
| Value | Description |
|---|---|
1 |
SENTx transmits data frame only when triggered using the SYNCTXEN status bit |
0 |
SENTx transmits data frames continuously while SNTEN = |
Bit 9 – TXPOL SENTx Transmit Polarity bit(1)
| Value | Description |
|---|---|
1 |
SENTx data output pin is low in the Idle state |
0 |
SENTx data output pin is high in the Idle state |
Bit 8 – CRCEN CRC Enable bit
Module in Receive Mode (RCVEN = 1):
1 = SENTx performs CRC verification on received data
using the preferred J2716 method
0 = SENTx does not perform CRC verification on received
data
Module in Transmit Mode (RCVEN = 1):
1 = SENTx automatically calculates CRC using the
preferred J2716 method
0 = SENTx does not calculate CRC
Bit 7 – PPP Pause Pulse Present bit
| Value | Description |
|---|---|
1 |
SENTx is configured to transmit/receive SENT messages with pause pulse |
0 |
SENTx is configured to transmit/receive SENT messages without pause pulse |
Bit 6 – SPCEN Short PWM Code Enable bit(2)
| Value | Description |
|---|---|
1 |
SPC control from external source is enabled |
0 |
SPC control from external source is disabled |
Bit 4 – PS SENTx Module Clock Prescaler (divider) bit
| Value | Description |
|---|---|
1 |
Divide-by-4 |
0 |
Divide-by-1 |
Bits 2:0 – NIBCNT[2:0] Nibble Count Control bits
| Value | Description |
|---|---|
111 |
Reserved; do not use |
110 |
Module transmits/receives six data nibbles in a SENT data pocket |
101 |
Module transmits/receives five data nibbles in a SENT data pocket |
100 |
Module transmits/receives four data nibbles in a SENT data pocket |
011 |
Module transmits/receives three data nibbles in a SENT data pocket |
010 |
Module transmits/receives two data nibbles in a SENT data pocket |
001 |
Module transmits/receives one data nibble in a SENT data pocket |
000 |
Reserved; do not use |