14.1 ADC Features Overview

The high-speed, 12-bit multiple SARs Analog-to-Digital Converter (ADC) includes the following features:

  • One Shared (common) Core
  • User-Configurable Resolution of Up to 12 Bits
  • Up to 3.5 Msps Conversion Rate per Channel at 12-Bit Resolution
  • Low Latency Conversion
  • Up to 28 Analog Input Channels with a Separate 16-Bit Conversion Result Register for each Input Channel
  • Conversion Result can be Formatted as Unsigned or Signed Data, on a per Channel Basis, for All Channels
  • Channel Scan Capability
  • Multiple Conversion Trigger Options, Including:
    • PWM triggers from CPU core
    • SCCP modules triggers
    • CLC modules triggers
    • External pin trigger event (ADTRG31)
    • Software trigger
  • Four Integrated Digital Comparators with Dedicated Interrupts:
    • Multiple comparison options
    • Assignable to specific analog inputs
  • Four Oversampling Filters with Dedicated Interrupts:
    • Provide increased resolution
    • Assignable to a specific analog input

Simplified block diagrams of the 12-bit ADC are shown in Figure 14-1 and Figure 14-2.

The analog inputs (channels) are connected through multiplexers and switches to the Sample-and-Hold (S&H) circuit of the ADC core. The core uses the channel information (the output format, the Measurement mode and the input number) to process the analog sample. When conversion is complete, the result is stored in the result buffer for the specific analog input, and passed to the digital filter and digital comparator if they were configured to use data from this particular channel. If multiple ADC inputs request conversion on the shared core, the module will convert them in a sequential manner, starting with the lowest order input.

The ADC provides each analog input the ability to specify its own trigger source. This capability allows the ADC to sample and convert analog inputs that are associated with PWM Generators operating on independent time bases.

Figure 14-1. ADC Module Block Diagram
Note:
  1. Band Gap Reference (VBG) is an internal analog input and is not available on device pins.
  2. Your particular device may have a different number of dedicated cores; see the device-specific data sheet, pinout figures or Table 1-1.
Figure 14-2. Shared Core Block Diagram(1)
Note:
  1. Check the device pinout diagram to verify if the pin is available on the specific device.