33.2 AC Characteristics and Timing Parameters

Figure 33-1. Load Conditions for Device Timing Specifications
Table 33-23. Capacitive Loading Requirements on Output Pins
Param
 No.SymbolCharacteristicMin.Typ.Max.UnitsConditions
DO50COSCOOSCO Pin——15pFIn XT and HS modes, when External Clock is used to drive OSCI
DO56CIOAll I/O Pins and OSCO——50pFEC mode
DO58CBSCLx, SDAx——400pFIn I2C mode
Figure 33-2. External Clock Timing
Table 33-24. External Clock Timing Requirements

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymCharacteristicMin.Typ.(1)Max.UnitsConditions
OS10FINExternal CLKI Frequency (External Clocks allowed only
in EC and ECPLL modes)DC—64MHzEC
Oscillator Crystal Frequency3.5—10MHzXT
10—32MHzHS
OS20TOSCTOSC = 1/FOSC15.6—DCns
OS25TCYInstruction Cycle Time(2)10—DCns
OS30TOSL,

TOSH

External Clock in (OSCI)
High or Low Time0.45 x TOSC—0.55 x TOSCnsEC
OS31TOSR,

TOSF

External Clock in (OSCI)
Rise or Fall Time——20nsEC
OS40TCKRCLKO Rise Time(3,4)—5.4—ns
OS41TCKFCLKO Fall Time(3,4)—6.4—ns
OS42GMExternal Oscillator 
Transconductance(3)2.7—4mA/VXTCFG[1:0] = 00, XTBST = 0
4—7mA/VXTCFG[1:0] = 00, XTBST = 1
4.5—7mA/VXTCFG[1:0] = 01, XTBST = 0
6—11.9mA/VXTCFG[1:0] = 01, XTBST = 1
5.9—9.7mA/VXTCFG[1:0] = 10, XTBST = 0
6.9—15.9mA/VXTCFG[1:0] = 10, XTBST = 1
6.7—12mA/VXTCFG[1:0] = 11, XTBST = 0
7.5—19mA/VXTCFG[1:0] = 11, XTBST = 1
Note:
  1. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  2. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under Standard Operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Minimum” values with an External Clock applied to the OSCI pin. When an External Clock input is used, the “Maximum” cycle time limit is “DC” (no clock) for all devices.
  3. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin.
  4. This parameter is characterized but not tested in manufacturing.
Table 33-25. PLL Clock Timing Specifications

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsConditions
OS50FPLLIPLL Voltage Controlled Oscillator (VCO) Input Frequency Range8(2)—64MHzECPLL, XTPLL modes
OS51FVCOOn-Chip VCO System Frequency400—1600MHz
OS52TLOCKPLL Start-up Time (Lock Time)—60—µs
Note:
  1. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
  2. Inclusive of FRC Tolerance Specification, Parameter F20a.
Table 33-26. Auxiliary PLL Clock Timing Specifications

Standard Operating Conditions: 3.0V to 3.6V 
(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsConditions
OS50FPLLIAPLL Voltage Controlled Oscillator (VCO) Input Frequency Range8(2)—64MHzECPLL, XTPLL modes
OS51FVCOOn-Chip VCO System Frequency400—1600MHz
OS52TLOCKAPLL Start-up Time (Lock Time)—125—µs
Note:
  1. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
  2. Inclusive of FRC Tolerance Specification, Parameter F20a.
Table 33-27. Internal FRC Accuracy

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param No.CharacteristicMin.Max.UnitsConditions
Internal FRC Accuracy @ FRC Frequency = 8 MHz(1)
F20aFRC-2(2)+2%-40°C ≤ TA ≤ 0°C
-1.5+1.5%-5°C ≤ TA ≤ +85°C
-2+2%+85°C ≤ TA ≤ +125°C
F22BFRC/LPRC-17+17%-40°C ≤ TA ≤ +125°C
Note:
  1. Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
  2. Due to the effect of aging, this value may drift by an additional -0.5% over the lifetime of the device
Figure 33-3. I/O Timing Characteristics
Table 33-28. I/O Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsConditions
DO31TIORPort Output Rise Time(2)—6.59.7ns
DO32TIOFPort Output Fall Time(2)—3.24.2ns
DI35TINPINTx Pin High or Low Time (input)20——ns
DI40TRBPCNx High or Low Time (input)2——TCY
Note:
  1. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  2. This parameter is characterized but not tested in manufacturing.
Figure 33-4. BOR and Master Clear Reset Timing Characteristics
Table 33-29. Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SY00TPUPower-up Period—200—µs
SY10TOSTOscillator Start-up Time—1024 TOSC——TOSC = OSCI period
SY13TIOZI/O High-Impedance from MCLR Low or Watchdog Timer Reset—1.5—µs
SY20TMCLRMCLR Pulse Width (low)2——µs
SY30TBORBOR Pulse Width (low)1——µs
SY35TFSCMFail-Safe Clock Monitor Delay—500900µs-40°C to +85°C
SY36TVREGVoltage Regulator Standby-to-Active mode Transition Time——40µsClock fail to BFRC switch
SY37TOSCDFRCFRC Oscillator Start-up Delay——15µsFrom POR event
SY38TOSCDLPRCLPRC Oscillator Start-up Delay——50µsFrom Reset event
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
Figure 33-5. High-Speed PWMx Module Fault Timing Characteristics
Figure 33-6. High-Speed PWMx Module Timing Characteristics
Table 33-30. High-Speed PWMx Module Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.Typ.Max.UnitsConditions
MP00FINPWM Input Frequency450—500MHzNote 2
MP10TFPWMPWMx Output Fall Time———nsSee Parameter DO32
MP11TRPWMPWMx Output Rise Time———nsSee Parameter DO31
MP20TFDFault Input ↓ to PWMx

I/O Change

——26nsPCI Inputs 19 through 22
MP30TFHFault Input Pulse Width8——ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Input frequency of 500 MHz is recommended for High-Resolution mode.
Table 33-31. SPIx Maximum Data/Clock Rate Summary

SPI Host

Transmit Only

(Half-Duplex)

SPI Host

Transmit/

Receive

(Full-Duplex)

SPI Client

Transmit/

Receive

(Full-Duplex)

CKE

Maximum

Data Rate (MHz)

Condition

Figure 33-7
Figure 33-8——015Using PPS
40Dedicated Pin
Figure 33-8
Table 33-32——115Using PPS
40Dedicated Pin
—Figure 33-9
Table 33-33—09Using PPS
40Dedicated Pin
—Figure 33-10
Table 33-34—19Using PPS
40Dedicated Pin
——Figure 33-11
Table 33-35015Using PPS
40Dedicated Pin
——Figure 33-12
Table 33-36115Using PPS
40Dedicated Pin
Figure 33-7. SPIx Host Mode (Half-Duplex, Transmit Only, CKE = 0) 
Timing Characteristics
Figure 33-8. SPIx Host Mode (Half-Duplex, Transmit Only, CKE = 1) 
Timing Characteristics
Table 33-32. SPIx Host Mode (Half-Duplex, Transmit Only) Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time———nsSee Parameter DO32 (Note 3)
SP21TSCRSCKx Output Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,
TSCL2DOVSDOx Data Output Valid After SCKx Edge—620ns
SP36TDIV2SCH,
TDIV2SCLSDOx Data Output Setup to First SCKx Edge30——nsUsing PPS pins
3——nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 33-9. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) 
Timing Characteristics
Table 33-33. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = X, SMP = 1) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time———nsSee Parameter DO32 (Note 3)
SP21TSCRSCKx Output Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After SCKx Edge—620ns
SP36TDOV2SC, TDOV2SCLSDOx Data Output Setup to First SCKx Edge30——nsUsing PPS pins
3——nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input to SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 33-10. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) 
Timing Characteristics
Table 33-34. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time———nsSee Parameter DO32 (Note 3)
SP21TSCRSCKx Output Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After SCKx Edge—620ns
SP36TDOV2SCH, TDOV2SCLSDOx Data Output Setup to
First SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP40TdiV2SCH, TdiV2SCLSetup Time of SDIx Data Input to SCKx Edge30——nsUsing PPS pins
10——nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 33-11. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) 
Timing Characteristics
Table 33-35. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolChar.(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Input Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP72TSCFSCKx Input Fall Time———nsSee Parameter DO32 (Note 3)
SP73TSCRSCKx Input Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After
 SCKx Edge—620ns
SP36TDOV2SCH, TDOV2SCLSDOx Data Output Setup to
 First SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
10——nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
SP50TSSL2SCH, TSSL2SCLSSx ↓ to SCKx ↑ or SCKx ↓ Input120——ns
SP51TSSH2DOZSSx ↑ to SDOx Output
High-Impedance8—50nsNote 3
SP52TSCH2SSH,

TSCL2SSH

SSx ↑ After SCKx Edge1.5 TCY + 40——nsNote 3
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 33-12. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) 
Timing Characteristics
Table 33-36. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Input 
Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP72TSCFSCKx Input Fall Time———nsSee Parameter DO32 (Note 3)
SP73TSCRSCKx Input Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After
 SCKx Edge—620ns
SP36TDOV2scH, TDOV2SCLSDOx Data Output Setup to
 First SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
10——nsSPI2 dedicated pins
SP41TSCH2diL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
SP50TSSL2SCH, TssL2scLSSx ↓ to SCKx ↑ or SCKx ↓ Input120——ns
SP51TSSH2doZSSx ↑ to SDOx Output
High-Impedance8—50nsNote 3
SP52TSCH2SSH,

TSCL2SSH

SSx ↑ After SCKx Edge1.5 TCY + 40——nsNote 3
SP60TSSL2DOVSDOx Data Output Valid After SSx Edge——50ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 33-13. I2Cx Bus Start/Stop Bits Timing Characteristics (Host Mode)
Figure 33-14. I2Cx Bus Data Timing Characteristics (Host Mode)
Table 33-37. I2Cx Bus Data Timing Requirements (Host Mode)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(4)Min.(1)Max.UnitsConditions
IM10Tlo:sclClock Low Time100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM11Thi:sclClock High Time100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM20Tf:sclSDAx and SCLx
Fall Time100 kHz mode—300nsCb is specified to be from 10 to 400 pF
400 kHz mode20 x (VDD/5.5V)300ns
1 MHz mode(2)—120ns
IM21Tr:sclSDAx and SCLx
Rise Time100 kHz mode—1000nsCb is specified to be from 10 to 400 pF
400 kHz mode20 + 0.1 Cb300ns
1 MHz mode(2)—120ns
IM25Tsu:datData Input
Setup Time100 kHz mode250—ns
400 kHz mode100—ns
1 MHz mode(2)50—ns
IM26Thd:datData Input
Hold Time100 kHz mode0—µs
400 kHz mode00.9µs
1 MHz mode(2)00.3µs
IM30Tsu:staStart Condition
Setup Time100 kHz modeTCY (BRG + 1)—µsOnly relevant for Repeated Start
condition
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM31Thd:staStart Condition Hold Time100 kHz modeTCY (BRG + 1)—µsAfter this period, the
 first clock pulse is
 generated
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM33Tsu:stoStop Condition Setup Time100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM34Thd:stoStop Condition

Hold Time

100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM40Taa:sclOutput Valid from Clock100 kHz mode—3450ns
400 kHz mode—900ns
1 MHz mode(2)—450ns
IM45Tbf:sdaBus Free Time100 kHz mode4.7—µsTime the bus must be free before a new
 transmission can start
400 kHz mode1.3—µs
1 MHz mode(2)0.5—µs
IM50CbBus Capacitive Loading—400pF
IM51TpgdPulse Gobbler Delay65390nsNote 3
Note:
  1. BRG is the value of the I2C Baud Rate Generator.
  2. Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
  3. Typical value for this parameter is 130 ns.
  4. These parameters are characterized but not tested in manufacturing.
Figure 33-15. I2Cx Bus Start/Stop Bits Timing Characteristics (Client Mode)
Figure 33-16. I2Cx Bus Data Timing Characteristics (Client Mode)
Table 33-38. I2Cx Bus Data Timing Requirements (Client Mode)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristic(3)Min.Max.UnitsConditions
IS10Tlo:sclClock Low Time100 kHz mode4.7—µs
400 kHz mode1.3—µs
1 MHz mode(1)0.5—µs
IS11Thi:sclClock High Time100 kHz mode4.0—µsDevice must operate at a minimum of 1.5 MHz
400 kHz mode0.6—µsDevice must operate at a minimum of 10 MHz
1 MHz mode(1)0.28—µs
IS20Tf:sclSDAx and SCLx
Fall Time100 kHz mode—300nsCb is specified to be from
 10 to 400 pF
400 kHz mode20 x (VDD/5.5V)300ns
1 MHz mode(1)20 x (VDD/5.5V)120ns
IS21Tr:sclSDAx and SCLx
Rise Time100 kHz mode20 + 0.1 Cb1000nsCb is specified to be from
 10 to 400 pF
400 kHz mode—300ns
1 MHz mode(1)—120ns
IS25Tsu:datData Input
Setup Time100 kHz mode250—ns
400 kHz mode100—ns
1 MHz mode(1)50—ns
IS26Thd:datData Input
Hold Time100 kHz mode0—µs
400 kHz mode00.9µs
1 MHz mode(1)00.3µs
IS30Tsu:staStart Condition
Setup Time100 kHz mode4.7—µsOnly relevant for Repeated Start condition
400 kHz mode0.6—µs
1 MHz mode(1)0.26—µs
IS31Thd:staStart Condition Hold Time100 kHz mode4.0—µsAfter this period, the first clock pulse is generated
400 kHz mode0.6—µs
1 MHz mode(1)0.26—µs
IS33Tsu:stoStop Condition Setup Time100 kHz mode4—µs
400 kHz mode0.6—µs
1 MHz mode(1)0.26—µs
IS34Thd:stoStop Condition

Hold Time

100 kHz mode> 0—µs
400 kHz mode> 0—µs
1 MHz mode(1)> 0µs
IS40Taa:sclOutput Valid from Clock100 kHz mode03540ns
400 kHz mode0900ns
1 MHz mode(1)0400ns
IS45Tbf:sdaBus Free Time100 kHz mode4.7—µsTime the bus must be free before a new transmission can start
400 kHz mode1.3—µs
1 MHz mode(1)0.5—µs
IS50CBBus Capacitive Loading—400pF
IS51TPGDPulse Gobbler Delay65390nsNote 2
Note:
  1. Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
  2. Typical value for this parameter is 130 ns.
  3. These parameters are characterized but not tested in manufacturing.
Figure 33-17. UARTx Module I/O Timing Characteristics
Table 33-39. UARTx Module I/O Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No.

SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
UA10TUABAUDUARTx Baud Time40——ns
UA11FBAUDUARTx Baud Frequency——15Mbps
UA20TCWFStart Bit Pulse Width to Trigger UARTx Wake-up50——ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Table 33-40. ADC Module Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(4)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicsMin.Typical(7)Max.UnitsConditions
Clock Requirements
AD9FSRC

ADC Module Input Frequency

——500MHz

Clock frequency selected by the CLKSELx bits

AD10FCORESRC

ADC Control Clock Frequency

——250MHz

Clock frequency after the first divider controlled by the CLKDIVx bits

AD11FADCORE

ADC SAR Core Clock Frequency

——70MHz

SAR core frequency after the second divider controlled by the ADCSx or SHRADCSx bits

Analog Input
AD12VINH – VINLFull-Scale Input SpanAVSS—AVDDV
AD14VINAbsolute Input VoltageAVSS – 0.3—AVDD + 0.3V
AD17RINRecommended Impedance of Analog Voltage Source—100—ΩFor minimum sampling time (Note 1)
AD60CHOLDCapacitance—5—pFDedicated cores (Note 1)
AD61CHOLDCapacitance—18—pFShared core (Note 1)
AD62RICInput resistance—5001000ΩIncludes RSS (Note 1)
AD66VBGInternal Voltage Reference Source1.141.21.26V
AD67FSRCADC Module Input Frequency——500MHzClock frequency selected by the CLKSELx bits
FCORESRCADC Control Clock Frequency——250MHzClock frequency after the first divider controlled by the CLKDIVx bits
FADCOREADC SAR Core Clock Frequency——70MHzSAR core frequency after the second divider controlled by the ADCSx or SHRADCSx bits
ADC Accuracy
AD20cNRResolution12 data bitsbits
AD21aINL_1D

Dedicated Core Integral Nonlinearity (1 Active Core)

-3.5-1.5/+1.5+3.5LSb3.5 Msps(5), TADC = 4 nS (250 MHz), TCORESRC = 8 nS (125 MHz), TADCORE = 16 nS (62.5 MHz), Sampling Time = 4 TADCORE, VDD = 3.3V, AVDD = 3.3V
AD22aDNL_1D

Dedicated Core Differential Nonlinearity (1 Active Core)

-1.0-1.5/+1.5+3.5LSb
AD23aGERR_1D

Dedicated Core Gain Error (1 Active Core)

—+4—LSb
AD24aOERR_1D

Dedicated Core Offset Error (1 Active Core)

—-4—LSb
AD21bINL _1S

Shared Core Integral Nonlinearity (1 Active Core)

-3.5-1.5/+1.5+3.5LSb2.7 Msps(6), TADC = 4 nS (250 MHz), TCORESRC = 8 nS (125 MHz), TADCORE = 16 nS (62.5 MHz), Sampling Time = 10 TADCORE, VDD = 3.3V, AVDD = 3.3V
AD22bDNL_1SShared Core Differential Nonlinearity (1 Active Core)-1.0-1.5/+1.5+3.5LSb
AD23bGERR_1S

Shared Core Gain Error (1 Active Core)

—+4—LSb
AD24bOERR_1S

Shared Core Offset Error (1 Active Core)

—-4—LSb
AD21cINL _5D

Dedicated Core Integral Nonlinearity (5 Active Cores)

—-8/+8—LSb3.5 Msps(5), TADC = 4 nS (250 MHz), TCORESRC = 8 nS (125 MHz), TADCORE = 16 nS (62.5 MHz), Sampling Time = 4 TADCORE, VDD = 3.3V, AVDD = 3.3V, all core conversions are started simultaneously
AD22cDNL_5D

Dedicated Core Differential Nonlinearity (5 Active Cores)

—-1.5/+3—LSb
AD23cGERR_5D

Dedicated Core Gain Error (5 Active Cores)

—+9.5—LSb
AD24cOERR_5D

Dedicated Core Offset Error (5 Active Cores)

—-9.5—LSb
AD21dINL _5S

Shared Core Integral Nonlinearity (5 Active Cores)

—-8/+8—LSb2.7 Msps(6), TADC = 4 nS (250 MHz), TCORESRC = 8 nS (125 MHz), TADCORE = 16 nS (62.5 MHz), Sampling Time = 10 TADCORE, VDD = 3.3V, AVDD = 3.3V, all core conversions are started simultaneously
AD22dDNL_5S

Shared Core Differential Nonlinearity (5 Active Cores)

—-1.5/+3—LSb
AD23dGERR_5S

Shared Core Gain Error (5 Active Cores)

—+9.5—LSb
AD24dOERR_5S

Shared Core Offset Error (5 Active Cores)

—-9.5—LSb
AD25c—Monotonicity———LSbGuaranteed
Dynamic Performance
AD31bSINADSignal-to-Noise and 
Distortion56—70dBNotes 2, 3
AD34bENOBEffective Number of Bits9.810.211.4bitsNotes 2, 3
AD50TADADC Clock Period14.3——ns
AD51FTPThroughput Rate——3.5Msps Dedicated cores
——2.7MspsShared core
Note:
  1. These parameters are not characterized or tested in manufacturing.
  2. These parameters are characterized but not tested in manufacturing.
  3. Characterized with a 1 kHz sine wave.
  4. The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is ensured, but not characterized.
  5. For the dedicated core, the throughput includes 4 TADCORE sampling time and 13 TADCORE conversion time.
  6. For the shared core, the throughput includes 10 TADCORE sampling time and 13 TADCORE conversion time.
  7. Data in the “Typical” column are at 3.3V, +25°C. Parameters are for design guidance only and are not tested.
Table 33-41. High-Speed Analog Comparator Module Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(2)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymbolCharacteristicMin.Typ.Max.UnitsComments
CM09FINInput Frequency400500550MHz
CM10VIOFFInput Offset Voltage-20—+20mV
CM11VICMInput Common-Mode 
Voltage Range(1)AVSS—AVDDVNote 1
CM13CMRRCommon-Mode 
Rejection Ratio60——dBNote 1
CM14TRESPLarge Signal Response—15—nsV+ input step of 100 mV while 
V- input is held at AVDD/2
CM15VHYSTInput Hysteresis153045mVDepends on HYSSEL[1:0] (Note 1)
Note:
  1. These parameters are for design guidance only and are not tested in manufacturing.
  2. The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
Table 33-42. Die Temperature Diode Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.Max.UnitsComments
TD01TCOEFF—1.5—mV/CNote 1
Note:
  1. These parameters are not characterized or tested in manufacturing.
Table 33-43. DACx Module Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsComments
DA02CVRESResolution12bits
DA03INLIntegral Nonlinearity Error-43—0LSB
DA04DNLDifferential Nonlinearity Error-5—5LSB
DA05EOFFOffset Error-3.5—25LSBInternal node at comparator input
DA06EGGain Error0—41%Internal node at comparator input
DA07TSETSettling Time6007502000nsOutput with 1% of desired output voltage with a 
5-95% or 95-5% step (Note 1)
DA08VOUTVoltage Output Range0.165—3.135VVDD = 3.3V
DA09TTRTransition Time340——nsNote 1
DA10TSSSteady-State Time550——nsNote 1
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
Table 33-44. DACx Output (DACOUT1 and DACOUT2 Pins) Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1,2,3)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.Max.UnitsComments
DA11RLOADResistive Output Load 
Impedance10K——Ohm
DA11aCLOADOutput Load Capacitance——30pFIncluding output pin capacitance
DA12IOUTOutput Current Drive Strength—3—mASink and source
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
  2. The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
  3. Using other pin functions may degrade DAC performance.
Table 33-45. Constant-Current Source Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicMin.Typ.Max.UnitsConditions
CC02IREGCurrent Regulation—±3—%IBIASx pin
CC03I10SRC10 µA Source Current8.8—11.2µAISRCx pin
CC04I50SRC50 µA Source Current44—56µAIBIASx pin
CC05I50SNK50 µA Sink Current-44—-56µAIBIASx pin
Note:
  1. The constant-current source module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
Table 33-46. Operational Amplifier Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymCharacteristicMinTyp(1)MaxUnitsComments
OA01GBWPGain Bandwidth Product—20—MHz
OA02SRSlew Rate—40—V/µs
OA03VIOFFInput Offset Voltage-3(3)-1/+1+3(3)mVUnity gain configuration
-8-3/+3+8mVOpen-loop configuration
OA04VIBCInput Bias Current———nANote 2
OA05VICMCommon-Mode Input Voltage RangeAVSS—AVDDVNCHDISx = 0
AVSS—AVDD – 1.4VNCHDISx = 1
OA07CMRRCommon-Mode Rejection Ratio—68—dB
OA08PSRRPower Supply Rejection Ratio—74—dB
OA09VOROutput Voltage RangeAVSS—AVDDmV0.5V input overdrive, no output loading (Note 1)
OA11CLOADOutput Load Capacitance——30pFIncluding output pin capacitance (Note 1)
OA12IOUTOutput Current Drive Strength—3—mASink and source (Note 1)
OA13PMARGINPhase Margin44——degreeUnity gain (Note 1)
OA14GMARGINGain Margin7——dBUnity gain (Note 1)
OA15OLGOpen-Loop Gain6875—dBNote 1
Note:
  1. These parameters are for design guidance only and are not tested in manufacturing.
  2. The op amps use CMOS input circuitry with negligible input bias current. The maximum “effective bias current” is the I/O pin leakage specified by electrical Parameter DI50.
  3. Parameters are characterized but not tested in manufacturing.
Figure 33-18. QEA/QEB Input Characteristics
Table 33-47. Quadrature Decoding Timing Requirements

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param.SymbolCharacteristic(1)Typ.(2)Max.UnitsConditions
TQ30TQULQuadrature Input Low Time 6 TCY—ns
TQ31TQUHQuadrature Input High Time

6 TCY

—ns
TQ35TQUINQuadrature Input Period

12 TCY

—ns
TQ36TQUPQuadrature Phase Period

3 TCY

—ns
TQ40TQUFLFilter Time to Recognize Low with Digital Filter

3 * N * TCY

—nsN = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3)
TQ41TQUFHFilter Time to Recognize High with Digital Filter

3 * N * TCY

—nsN = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3)
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
  3. N = Index Channel Digital Filter Clock Divide Select bits. Refer to “Quadrature Encoder Interface (QEI)” (DS70000601) in the “dsPIC33E/PIC24E Family Reference Manual.” Please see the Microchip web site for the latest family reference manual sections.
Figure 33-19. QEI Module Index Pulse Timing Characteristics
Table 33-48. QEI Index Pulse Timing Requirements

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param.SymbolCharacteristic(1)Typ.(2)Max.UnitsConditions
TQ50

TQIL

Filter Time to Recognize Low with Digital Filter 3 * N * TCY—ns

N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2)

TQ51

TQIH

Filter Time to Recognize High with Digital Filter 3 * N * TCY—ns

N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2)

TQ55

TQIDXR

Index Pulse Recognized to Position Counter Reset (ungated index)

3 TCY

—ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). The same timing applies for reverse direction (QEA lags QEB), but index pulse recognition occurs on the falling edge.
Figure 33-20. QEI External Clock Timing Characteristics
Table 33-49. QEI Module External Clock Timing Requirements

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param.SymbolCharacteristic(1)Typ.Max.UnitsConditions
TQ10TTQH

TQCK High Time

Synchronous, with Prescaler——nsMust also meet Parameter TQ15
TQ11TTQL

TQCK Low Time

Synchronous, with Prescaler——nsMust also meet Parameter TQ15
TQ15TTQP

TQCP Input Period

Synchronous, with Prescaler——ns
TQ20TCKEXTMRL

Delay from External TxCK Clock Edge to Timer Increment

1TCY—
Note:
  1. These parameters are characterized but not tested in manufacturing.