6.3 SPI Clock Configuration
The SPI clock configuration used for communication between the core and Secure Subsystem is as follows:
- For communication in Mode 0, CKP =
0
, CKE =1
. - For communication in Mode 3, CKP
=
1
, CKE =0
.
Note:
- All the connections are internal to the device. The corresponding PPS registers must be configured to establish communication with the Secure Subsystem.
- Refer to RPOR13 for more information on configuring the PPS register.
- The corresponding SDIxR register bits of SPI should be set to 52.
- Refer to RPOR10 for more information on configuring the PPS register.
- RE12 I/O pin is not available for general purpose and its associated I/O registers are available only for communication with the Secure Subsystem.
- Ensure that the SPI signals are not left floating to avoid unintended current consumption.