3.10.2.7.1.3 EIMSK –
External Interrupt Mask Register
| Name: | EIMSK |
| Offset: | 0x027 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | INT1 | INT0 | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – INT1 External Interrupt
Request 1 Enable
When the INT1 bit is set
(‘1’) and the I bit in the status register (SREG) is set
(‘1’), the external pin interrupt is enabled. The interrupt
sense control 1 bits (ISC11 and ISC10) in the external interrupt control register A
(EICRA) define whether the external interrupt is activated on rising and/or falling
edge of the INT1 pin or the level is sensed. Activity on the pin causes an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of
External Interrupt Request 1 is executed from the INT1 Interrupt
Vector.
Bit 0 – INT0 External Interrupt
Request 0 Enable
When the INT0 bit is set
(‘1’) and the I bit in the status register (SREG) is set
(‘1’), the external pin interrupt is enabled. The interrupt
sense control 0 bits (ISC01 and ISC00) in the external interrupt control register A
(EICRA) define whether the external interrupt is activated on the rising and/or
falling edge of the INT0 pin or the level is sensed. Activity on the pin causes an
interrupt request even if INT0 is configured as an output. The corresponding
interrupt of external interrupt request 0 is executed from the INT0 interrupt
vector.
