3.10.2.7.1.6 PCIFR – Pin Change
Interrupt Flag Register
| Name: | PCIFR |
| Offset: | 0x00F |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | PCIF1 | PCIF0 | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and reads
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 1 – PCIF1 Pin Change
Interrupt Flag 1
When a logic change on any
PCINT[13:8] (PORT C) pin triggers an interrupt request, PCIF1 becomes set
(‘1’). If the I-bit in SREG and the PCIE1 bit in PCICR are set
(‘1’), the MCU jumps to the corresponding interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can
be cleared by writing a logical ‘1’ to it.
Bit 0 – PCIF0 Pin Change Interrupt Flag 0
When a logic change on any
PCINT[7:0] (PORT B) pin triggers an interrupt request, PCIF0 becomes set
(‘1’). If the I-bit in SREG and the PCIE0 bit in PCICR are set
(‘1’), the MCU jumps to the corresponding interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can
be cleared by writing a logical ‘1’ to it.
