3.10.2.7.1.2 EICRA – External Interrupt Control Register A


Bit	7	6	5	4	3	2	1	0
					ISC11	ISC10	ISC01	ISC00
Access	R	R	R	R	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 6 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 5 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 4 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 3 – ISC11 External Interrupt 1 Sense Control Bit

The External Interrupt 1 is activated by the external pin INT1 if the SREG I flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activates the interrupt are defined in the following table. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses longer than one clock period generate an interrupt. Shorter pulses may generate an interrupt, but not necessarily. If the low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Table 3-65. Interrupt INT1 Sense Control
ISC11	ISC10	Description
`0`	`0`	The low level of INT1 generates an interrupt request.
`0`	`1`	Any logical change on INT1 generates an interrupt request.
`1`	`0`	The falling edge of INT1 generates an interrupt request.
`1`	`1`	The rising edge of INT1 generates an interrupt request.

Note: When changing the ISC11/ISC10 bits, the interrupt must be disabled by clearing its interrupt enable bit in the EIMSK register. Otherwise, an interrupt can occur when the bits are changed.

Bit 2 – ISC10

Refer to ISC11 bit description.

Bit 1 – ISC01 External Interrupt 0 Sense Control Bit

The external interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activates the interrupt are defined in the following table. The value on the INT0 pin is sampled before detecting edges. If an edge or toggle interrupt is selected, pulses that last longer than one clock period generate an interrupt. Shorter pulses may generate an interrupt, but not necessarily. If the low level interrupt is selected, to generate an interrupt the low level must be held until the completion of the currently executing instruction.

Table 3-66. Interrupt INT0 Sense Control
ISC01	ISC00	Description
`0`	`0`	The low level of INT0 generates an interrupt request.
`0`	`1`	Any logical change on INT0 generates an interrupt request.
`1`	`0`	The falling edge of INT0 generates an interrupt request.
`1`	`1`	The rising edge of INT0 generates an interrupt request.

Note: When changing the ISC01/ISC00 bits, the interrupt must be disabled by clearing its interrupt enable bit in the EIMSK register. Otherwise, an interrupt can occur when the bits are changed.

Bit 0 – ISC00

Refer to ISC01 bit description.

Name:	EICRA
Offset:	0x06B
Reset:	0x00