3.10.2.7.1.5 PCICR – Pin
Change Interrupt Control Register
| Name: | PCICR |
| Offset: | 0x026 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | PCIE1 | PCIE0 | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – PCIE1 Pin Change
Interrupt Enable 1
When the PCIE1 bit is set to
‘1’ and the I-bit in the status register (SREG) is set to
‘1’, the pin change interrupt 1 is enabled. Any change on any
enabled PCINT14..8 pin will cause an interrupt. The corresponding interrupt of the
pin change interrupt request is executed from the PCI1 interrupt vector. PCINT13..8
pins are enabled individually in the PCMSK1 register.
Bit 0 – PCIE0 Pin Change
Interrupt Enable 0
When the PCIE0 bit is set to
‘1’ and the I-bit in the status register (SREG) is set to
‘1’, the pin change interrupt 0 is enabled. Any change on any
enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of the
pin change interrupt request is executed from the PCI0 interrupt vector. PCINT7..0
pins are enabled individually in the PCMSK0 register.
