3.10.2.7.1.4 EIFR – External
Interrupt Flag Register
| Name: | EIFR |
| Offset: | 0x028 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | INTF1 | INTF0 | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – INTF1 External Interrupt
Flag 1
When an edge or logic change
on the INT1 pin triggers an interrupt request, INTF1 becomes set
(‘1’). If the I-bit in SREG and the INT1 bit in EIMSK are set
(‘1’), the MCU jumps to the corresponding interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can
be cleared by writing a logical ‘1’ to it. This flag is always
cleared (kept at ‘0’) when INT0 is configured as a level
interrupt.
Bit 0 – INTF0 External Interrupt
Flag 0
When an edge or logic change
on the INT0 pin triggers an interrupt request, INTF0 becomes set
(‘1’). If the I-bit in SREG and the INT0 bit in EIMSK are set
(‘1’), the MCU jumps to the corresponding interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can
be cleared by writing a logical ‘1’ to it. This flag is always
cleared (kept at ‘0’) when INT0 is configured as a level
interrupt.
