3.10.7.1.1.3 T0IFR – Timer0
Interrupt Flag Register
| Name: | T0IFR |
| Offset: | 0x02F |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | T0F | |
| Access | R | R | R | R | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – T0F Timer0
Flag
When the interval timer in
Timer0 generates an output clock pulse (CLKT0), the T0F bit is set
(‘1’). If the I-bit in SREG and the T0IE bit is set
(‘1’) in T0CR, the MCU jumps to the corresponding interrupt
vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag can be cleared by writing a logical ‘1’ to
it.
