3.10.7.1.1.2 T0CR – Timer0 Control Register
| Name: | T0CR |
| Offset: | 0x010 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T0PR | T0IE | T0PS[2:0] | |||||||
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
0’.Bit 6 – Reserved Bit
0’.Bit 5 – Reserved Bit
0’.Bit 4 – T0PR Timer0 Prescaler Reset
1’ restarts the watchdog prescaler. Once written to
‘1’, the hardware clears this bit after four clock cycles. Only
if the watchdog function is disabled can the watchdog prescaler be
restarted.Bit 3 – T0IE Timer0 Interrupt Enable
1’ enables an interval timer interrupt if the I bit in SREG is
set. Writing T0IE to ‘0’ disables the interrupt. The corresponding
interrupt vector is executed when the T0F flag, located in T0FR, is
set.Bits 2:0 – T0PS[2:0] Timer0 Prescaler Select
|
T0PS2 |
T0PS1 |
T0PS0 |
Number of Oscillator Cycles (CLKSRC) |
Typical Time-out at TSRC 1/125KHz for CLKT0 |
|---|---|---|---|---|
0 | 0 | 0 | 32 cycles | 0.256 ms |
0 | 0 | 1 | 128 cycles | 1 ms |
0 | 1 | 0 | 1K cycles | 8 ms |
0 | 1 | 1 | 64K cycles | 0.5s |
1 | 0 | 0 | 128K cycles | 1s |
1 | 0 | 1 | 1M cycles | 8s |
1 | 1 | 0 | 8M cycles | 67s |
1 | 1 | 1 | 16M cycles | 134s |