3.10.7.1.1.1 WDTCR – Watchdog Timer0 Control Register


Bit	7	6	5	4	3	2	1	0
				WDCE	WDE	WDPS[2:0]
Access	R	R	R	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 6 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 5 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 4 – WDCE Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit and/or change the prescaler bits, WDCE has to be set. Once written to ‘1’, the hardware clears WDCE after four clock cycles.

Bit 3 – WDE Watchdog Enable

The watchdog timer is enabled if the WDE bit is ‘1’. If the WDE is written to logic ‘0’, the watchdog timer function is disabled. WDE can only be cleared if the WDCE bit has logic level ‘1’. The following procedure must be followed to disable an enabled watchdog timer. In the same operation, write a logic ‘1’ to WDCE and WDE. A logic ‘1’ must be written to WDE even though it is set to ‘1’ before the disable operation starts. Within the next four clock cycles, write a logic ‘0’ to WDE. This disables the watchdog. In safety level 2, it is not possible to disable the watchdog timer, even with the algorithm described above. WDE is overridden by WDRF in the MCUSR. This means the WDE is always set when the WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure and a safe start-up after the failure.

Bits 2:0 – WDPS[2:0] Watchdog Prescaler Select

The WDPS[2:0] bits determine the watchdog timer prescaling clock output (CLKWD) when the watchdog timer is enabled. The time-out value after a watchdog reset command (WDR) is not precisely known because the WDR command resets only the watchdog divider. The watchdog prescaler is shared by the watchdog and Timer0 and, therefore, continues counting. For this reason, a typical and minimum ensured time-out period is given in the following table.

Table 3-88. Watchdog Timer Prescaler Select Bit Description
WDPS[2:0]			Prescaler Divider Values (Number of CLK_SRC Cycles)	Total Numbers of CLK_SRC Cycles Including Watchdog Divider	Time-out at VCC=3V/25°C and T_SRC≈ 1/125 KHz
WDPS[2:0]			Prescaler Divider Values (Number of CLK_SRC Cycles)	Total Numbers of CLK_SRC Cycles Including Watchdog Divider	Typical	Minimum
`0`	`0`	`0`	16 cycles	8 x 16 = 128 cycles	1 ms	0.85 ms
`0`	`0`	`1`	64 cycles	8 x 64 = 512 cycles	4 ms	3.4 ms
`0`	`1`	`0`	512K cycles	8 x 512 = 4K cycles	32 ms	27 ms
`0`	`1`	`1`	32K cycles	8 x 32K = 256K cycles	2.1s	1.75s
`1`	`0`	`0`	64K cycles	8 x 64K = 512K cycles	4.2s	3.5s
`1`	`0`	`1`	256K cycles	8 x 256K = 2M cycles	16.8s	14s
`1`	`1`	`0`	2M cycles	8 x 2M = 16M cycles	134s	110s
`1`	`1`	`1`	4M cycles	8 x 4M = 32M cycles	268s	220s

Name:	WDTCR
Offset:	0x06E
Reset:	0x00