3.10.4.4.1 CLKOCR – Clock
Output Control Register
| Name: | CLKOCR |
| Offset: | 0x0C4 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | CLKOEN | CLKOS[1:0] | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 2 – CLKOEN Enable Clock Output
Driver to CLK_OUT
The corresponding data
direction register of the port has to be set as output to enable the driver. The
CLK_OUT prescaler settings (CLKOCR.CLKOS and CLKOD) can be modified only if the
clock output is disabled (CLKOCR.CLKOEN = 0).
Bits 1:0 – CLKOS[1:0] Clock Output
Source
Selects the reference clock
for the CLK_OUT divider, as described in the following table. This clock output
source can be modified only if the clock output is disabled (CLKOCR.CLKOEN =
0).
Table 3-70. CLKOS - Clock Output
Clock Source Selection| CLKOS[1:0] | Clock Source |
|---|
0 | 0 | CLKSRC |
0 | 1 | CLKFRC |
1 | 0 | Reserved |
1 | 1 | CLKXTO |
