3.10.4.4.8 CMIMR – Clock
Management Interrupt Mask Register
| Name: | CMIMR |
| Offset: | 0x03A |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | ECIE | |
| Access | R | R | R | R | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – ECIE External Clock Interrupt Enable
Writing ECIE to
‘1’ enables the clock monitoring interrupt vector if the I bit
in SREG is set. The corresponding interrupt vector is executed when the CMSR.ECF
flag is set. Writing ECIE to ‘0’ disables the
interrupt.
