3.10.4.4.7 CMSR – Clock
Management Status Register
| Name: | CMSR |
| Offset: | 0x0C8 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | ECF | |
| Access | R | R | R | R | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – ECF External Clock
Fail
This bit is set if the
clock-monitoring circuit detects a breakdown of the external input clock
(CLKEXT). ECF is automatically cleared when the clock monitoring
interrupt vector is executed. Alternatively, ECF can be cleared by writing a logic
‘1’ to its bit location.
