13.17.1 Voltage Supervisor

The voltage supervisor protects the MOSFET Gate Driver, external power MOSFETs and the host dsPIC DSC from damage due to overvoltage or undervoltage of the input supply, HVDD.

In the event of an undervoltage condition HVDD < UVLOACT, overvoltage condition, HVDD > UVLOACT or VREG LDO undervoltage condition VREG < VREGUVFACT, the gate drivers, charge pump and VBOOT regulator are switched off. The bias generator, communication po rt, operational amplifiers and the remainder of the motor control unit remain active. The Failure state is flagged on the FAULT pin, and a DE2 status message is sent.

In extreme overvoltage conditions, HVDD > OVSHDNACT, the VREG LDO will be shut down as soon as pin OE is set to a low level. The OVSHDN status flag in the STAT0 register will be set and will remain set until the register is read by a host. The DE2 communications link will be disabled together with the VREG LDO. No Fault message will be sent to the host because the device must shut down immediately to prevent high-voltage damage. The VREG LDO will be re-enabled when the HVDD supply voltage drops below the Overvoltage Lockout value, OVLOINACT.

In the event of a severe undervoltage condition, HVDD < UVSHDNACT, the entire device will shut down except for the minimal circuitry required for a Power-on Reset recovery. A UVSHDN Fault will be set. The VREG output will be turned off and pulled low to create a “clean” shutdown of an attached host processor. The Undervoltage Shutdown condition is a Latched state. The state machine will be restarted from the Power-on Reset state when either of the following two conditions are met:

  1. HVDD power is cycled.
  2. HVDD rises above UVLOINACT (6.0V).